Memory devices, such as random access memories (RAMs) and read only memories (ROMs) can access single entries according to applied addresses. However, other types of memory devices can provide a matching function with respect to all entries in the device. One such type of memory device is a content addressable memory (CAM) device.
CAM devices can provide a rapid comparison between a specific pattern of received data bits, commonly known as a search key or comparand, and data values stored in an associative CAM memory array to provide a match or no-match result. If every bit in a group of CAM memory cells matches corresponding bits in the comparand, a match flag can indicate a match condition via a match line, for example. In this way, a user can be notified that the data in the comparand was found in memory and a value corresponding to the match can be returned. Thus, in a CAM device, as result can be determined from finding a matching value (content), not from providing the address of the value as done for a RAM or ROM.
Generally, there are two types of CAM cells typically used in conventional CAM arrays: binary CAM cells and ternary CAM (TCAM) cells.
Binary CAM cells can store either a logic high bit value or a logic low bit value. When the logic value stored in the binary CAM cell matches a data bit from an applied comparand, the CAM cell can provide a high impedance path with respect to a match line, and the match line can be maintained at a logic high value (assuming all other CAM cells electrically connected to the match line also match the comparand). In this way, a match (HIT) result can be indicated. However, when the logic value stored in the binary CAM cell does not match the data bit from the applied comparand, the CAM cell can provide a low impedance path between ground and the match line, and the match line can be pulled low. In this way, a no match (MISS) result can be indicated.
Conventional TCAM cells can store three bit values that can represent three different states: a logic high value, a logic low value, and a “don't care” value. When storing logic high and logic low values, a conventional TCAM cell can operate like a binary CAM cell as described above. However, a TCAM cell storing a “don't care” value can provide a match condition for any data bit value from a comparand applied to that TCAM cell.
An exemplary embodiment of an existing TCAM cell is set forth in FIG. 9 in a circuit schematic diagram and given the general reference character 900.
Conventional TCAM cell 900 includes an X-cell 910, a Y-cell 920, and a compare circuit 930. Conventional TCAM cell 900 can have complementary bit lines (B1 and BB1) as inputs to Y-cell 920, and complementary bit lines (B2 and BB2) as inputs to X-cell 910. X-cell 910 and Y-cell 920 can receive a word line WL as a common input. Compare circuit 930 receives complementary compare data values (CD and BCD) as inputs, as well as X-cell stored data and Y-cell stored data at inputs YD and XD, respectively. Compare circuit 930 can provide a match output at match line ML.
X-cell 910 and Y-cell 920 can be essentially static random access memory (SRAM) cells having two inverters and two pass transistors. Compare circuit 930 can have two serially connected transistors providing the X-cell compare and two serially connected transistors providing the Y-cell compare.
Conventional TCAM cell 900 can have six lines that run vertically. These six lines can be the complementary bit lines (B1, BB1, BB2, and B2) and lines that carry complementary compare data (CD and BCD). Such use of six lines can be necessary to provide writing flexibility. More particularly, such a six line arrangement can be provided to support “non-atomic” writes, bit-wise maskable writes, or bit maskable parallel writes. Non-atomic writes can refer to writing different values to the separate SRAM cells (e.g., X-cell 910 or Y-cell 920) of TCAM cell 900. Bit maskable can refer to the ability to write to a first bit (BIT1) to a TCAM cell (X-cell X1, Y-cell Y1) in a word including or made up of a number of cells in a row, without writing a second bit (BIT2) to a TCAM cell (X-cell X2, Y-cell Y2) in the same row. Parallel writes can refer to writing a value to the same bit locations of multiple rows.